::"C synthesis"



High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior.<ref name='Springer Book'>Springer Book High Level Synthesis From Algorithm to Digital Circuit ISBN 978-1-4020-8587-1</ref> Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages.,<ref name='Martin09'>IEEE Xplore High-Level Synthesis: Past, Present, and Future DOI 10.1109/MDT.2009.83</ref> although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/Matlab. The code is analyzed, architecturally constrained, and scheduled to create a register-transfer level (RTL) hardware description language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.<ref name='eetimes'>EETimes The 'why' and 'what' of algorithmic synthesis</ref>

Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation.<ref> UBS University, France C-Based Rapid Prototyping for Digital Signal Processing</ref> The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.

"C synthesis" sections